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<title>ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values </title></head>
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<h1>ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F 56 /r</p>
<p>ORPS xmm1, xmm2/m128</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE</td>
<td>Return the bitwise logical OR of packed single-precision floating-point values in xmm1 and xmm2/mem</td></tr>
<tr>
<td>
<p>VEX.NDS.128.0F 56 /r</p>
<p>VORPS xmm1,xmm2, xmm3/m128</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Return the bitwise logical OR of packed single-precision floating-point values in xmm2 and xmm3/mem</td></tr>
<tr>
<td>
<p>VEX.NDS.256.0F 56 /r</p>
<p>VORPS ymm1, ymm2, ymm3/m256</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Return the bitwise logical OR of packed single-precision floating-point values in ymm2 and ymm3/mem</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.0F.W0 56 /r</p>
<p>VORPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512DQ</p></td>
<td>Return the bitwise logical OR of packed single-precision floating-point values in xmm2 and xmm3/m128/m32bcst subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.0F.W0 56 /r</p>
<p>VORPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512DQ</p></td>
<td>Return the bitwise logical OR of packed single-precision floating-point values in ymm2 and ymm3/m256/m32bcst subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.0F.W0 56 /r</p>
<p>VORPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512DQ</td>
<td>Return the bitwise logical OR of packed single-precision floating-point values in zmm2 and zmm3/m512/m32bcst subject to writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Performs a bitwise logical OR of the four, eight or sixteen packed single-precision floating-point values from the first source operand and the second source operand, and stores the result in the destination operand</p>
<p>EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are zeroed.</p>
<p>VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.</p>
<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.</p>
<p><strong>Operation</strong></p>
<p><strong>VORPS (EVEX encoded versions)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF (EVEX.b == 1) AND (SRC2 *is memory*)</p>
<p>THEN</p>
<p>DEST[i+31:i] (cid:197) SRC1[i+31:i] BITWISE OR SRC2[31:0]</p>
<p>ELSE</p>
<p>DEST[i+31:i] (cid:197) SRC1[i+31:i] BITWISE OR SRC2[i+31:i]</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE *zeroing-masking*</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VORPS (VEX.256 encoded version)</strong></p>
<p>DEST[31:0] (cid:197) SRC1[31:0] BITWISE OR SRC2[31:0]</p>
<p>DEST[63:32] (cid:197) SRC1[63:32] BITWISE OR SRC2[63:32]</p>
<p>DEST[95:64] (cid:197) SRC1[95:64] BITWISE OR SRC2[95:64]</p>
<p>DEST[127:96] (cid:197) SRC1[127:96] BITWISE OR SRC2[127:96]</p>
<p>DEST[159:128] (cid:197) SRC1[159:128] BITWISE OR SRC2[159:128]</p>
<p>DEST[191:160] (cid:197) SRC1[191:160] BITWISE OR SRC2[191:160]</p>
<p>DEST[223:192] (cid:197) SRC1[223:192] BITWISE OR SRC2[223:192]</p>
<p>DEST[255:224] (cid:197) SRC1[255:224] BITWISE OR SRC2[255:224].</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p><strong>VORPS (VEX.128 encoded version)</strong></p>
<p>DEST[31:0] (cid:197) SRC1[31:0] BITWISE OR SRC2[31:0]</p>
<p>DEST[63:32] (cid:197) SRC1[63:32] BITWISE OR SRC2[63:32]</p>
<p>DEST[95:64] (cid:197) SRC1[95:64] BITWISE OR SRC2[95:64]</p>
<p>DEST[127:96] (cid:197) SRC1[127:96] BITWISE OR SRC2[127:96]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>ORPS (128-bit Legacy SSE version)</strong></p>
<p>DEST[31:0] (cid:197) SRC1[31:0] BITWISE OR SRC2[31:0]</p>
<p>DEST[63:32] (cid:197) SRC1[63:32] BITWISE OR SRC2[63:32]</p>
<p>DEST[95:64] (cid:197) SRC1[95:64] BITWISE OR SRC2[95:64]</p>
<p>DEST[127:96] (cid:197) SRC1[127:96] BITWISE OR SRC2[127:96]</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VORPS __m512 _mm512_or_ps ( __m512 a, __m512 b);</p>
<p>VORPS __m512 _mm512_mask_or_ps ( __m512 s, __mmask16 k, __m512 a, __m512 b);</p>
<p>VORPS __m512 _mm512_maskz_or_ps (__mmask16 k, __m512 a, __m512 b);</p>
<p>VORPS __m256 _mm256_mask_or_ps (__m256 s, ___mmask8 k, __m256 a, __m256 b);</p>
<p>VORPS __m256 _mm256_maskz_or_ps (__mmask8 k, __m256 a, __m256 b);</p>
<p>VORPS __m128 _mm_mask_or_ps ( __m128 s, __mmask8 k, __m128 a, __m128 b);</p>
<p>VORPS __m128 _mm_maskz_or_ps (__mmask8 k, __m128 a, __m128 b);</p>
<p>VORPS __m256 _mm256_or_ps (__m256 a, __m256 b);</p>
<p>ORPS __m128 _mm_or_ps (__m128 a, __m128 b);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type 4.</p>
<p>EVEX-encoded instruction, see Exceptions Type E4.</p></body></html>